This disclosure relates generally to three-dimensional integrated circuit design, and more specifically, to converting 3D integrated circuit design images to an equivalent two-dimensional technology design to perform design checks validating intra-chip and inter-chip connections of the original 3D design.
An integrated circuit (IC) is a semiconductor device that includes many electronic components (transistors for example). These components may be interconnected to form multiple circuit components such as gate cells, decoders, and controllers on the IC.
Design engineers design IC's by transforming circuit descriptions of an IC into geometric descriptions called a circuit layout. More specifically, a circuit designer begins by creating a functional block diagram depicting the logic design of the circuit (typically shown as inputs intersecting at “AND”, “OR”, and “NOR” gates). The functional block diagram is then translated into a schematic. The schematic contains the number and type of various circuit components, represented by distinct symbols, necessary to perform the logic design. The schematic is also typically accompanied by the necessary electrical parameters (i.e., voltage, current, resistance). It is from the schematic that the circuit layout may be designed, for example, by using a computer automated design (CAD) program or other electronic design automation (EDA) applications. In the circuit layout, each circuit component from the schematic is translated into a physical shape and size to form a composite picture of the circuit. A circuit layout may also be referred to as a cell or a design cell. The circuit layout is analogous to a blue print for the circuit. Not every cell needs to be designed from scratch. Many EDA applications have access to Cell Libraries, which have descriptions and layouts that can be used to accomplish various logic designs.
The composite picture shows the circuit in three dimensions as the interconnections of the circuit may traverse multiple layers (this is distinguishable from a three dimensional chip, which will be discussed subsequently). As the building of the three dimensional circuit on a chip takes place one layer at a time, the composite picture is separated into individual layers in the circuit. Each individual layer drawing is then digitized and plotted on an x-y plotting table. Each digitized layer pattern may be used to produce a mask or reticle, or series of masks and/or reticles, to etch and print the layers and corresponding circuit components on semiconductor wafers. The constructed circuit duplicates the circuit layout (design cell). The completed semiconductor devices are now known as chips which may be joined to a carrier on the I/O chip surface. Those skilled in the art will recognize that a “chip” may refer to either a die or a wafer.
The broadly discussed steps of the IC design process may entail various operations. Some of the physical design operations that an EDA tool performs to obtain IC layouts include: (1) floorplanning, which finds the alignment and relative orientation of circuit components; (2) circuit placement; and (3) routing, which completes component interconnects. A completed layout is subject to verification processes, which check the layout to ensure design and functional requirements. Common verification processes include design rule checking (DRC) which determines if the layout satisfies a series of recommended parameters, and layout versus schematic (LVS) which determines whether the layout corresponds to the original schematic. These verification processes may be performed both to the entire composite picture of the circuit layout and to the separated individual layers.
It is upon the completion of the verification processes that the separated individual layer drawings are digitized, plotted, and used for mask creation.
Computer-based tools for creating, editing, analyzing, and checking IC design layouts are based on two dimensional chip technology. “Two-dimensional chip technology” refers to chip fabrication having design shapes (circuits and layers) on only one wafer surface. The circuits on a 2D chip are still in three dimensions.
Three dimensional (3D) chip technologies, on the other hand, incorporate a through silicon via (TSV) that passes through the substrate of an integrated circuit chip. The TSV allows for circuit designs to expand to the front and back wafer surface. Designs on both silicon wafer surfaces allow for one IC chip to join with another IC chip, introducing the concept of stacked chips (hence 3D chip technology). In 3D, the first chip may connect to a carrier at one surface and connect to another chip at the second surface. IC chips may be stacked connecting to chips above and below, and the last chip of such a stack may connect to a heat sink.
Fundamental to 3D technology is that in order to connect a circuit design on one side of a chip to a circuit design on the other side of the chip, one of the circuit designs must be mirrored. Furthermore, as stacked chips may be connected face-to-face, face-to-back, and even back-to-back, where two separate chips connect, one of the connecting sides must mirror the other. Design tools for creating and checking multi-layer designs assume that all designs are on a single surface of a wafer. A typical checking environment provides the designer a top down design view and, again, assumes a single surface design. In current 3D technology, after the circuit layout is designed and verified, the design layers (the separated individual layers of a circuit layout) are mirrored to create new design layers (and ultimately a mirrored circuit layout/design cell). The new design layers are also digitized and turned into masks and/or reticles to create mirrored surfaces on 3D chips. These new design layers are not amenable to verification processes of existing design tools.